Go to the documentation of this file. 47 #define AMCC_OP_REG_OMB1 0x00 // Outgoing Mail Box 1 48 #define AMCC_OP_REG_OMB2 0x04 // Outgoing Mail Box 2 49 #define AMCC_OP_REG_OMB3 0x08 // Outgoing Mail Box 3 50 #define AMCC_OP_REG_OMB4 0x0C // Outgoing Mail Box 4 51 #define AMCC_OP_REG_IMB1 0x10 // Incoming Mail Box 1 52 #define AMCC_OP_REG_IMB2 0x14 // Incoming Mail Box 2 53 #define AMCC_OP_REG_IMB3 0x18 // Incoming Mail Box 3 54 #define AMCC_OP_REG_IMB4 0x1C // Incoming Mail Box 4 55 #define AMCC_OP_REG_FIFO 0x20 // FIFO Register 56 #define AMCC_OP_REG_MWAR 0x24 // Master Write Address Register 57 #define AMCC_OP_REG_MWTC 0x28 // Master Write Transfer Count Register 58 #define AMCC_OP_REG_MRAR 0x2C // Master Read Address Register 59 #define AMCC_OP_REG_MRTC 0x30 // Master Read Transfer Count Register 60 #define AMCC_OP_REG_MBEF 0x34 // Mailbox Empty/Full Status 61 #define AMCC_OP_REG_INTCSR 0x38 // Interrupt Control/Status Register 62 #define AMCC_OP_REG_MCSR 0x3C // Bus Master Control/Status Register 64 #define AMCC_OP_REG_RANGE_S5933 0x40 // number of operation registers 72 #define AMCC_OP_REG_OMB 0x0C // Outgoing Mail Box 73 #define AMCC_OP_REG_IMB 0x1C // Incoming Mail Box 74 #define AMCC_OP_REG_MBEF 0x34 // Mailbox Empty/Full Status 75 #define AMCC_OP_REG_INTCSR 0x38 // Interrupt Control/Status Register 76 #define AMCC_OP_REG_RCR 0x3C // Reset Control Register 77 #define AMCC_OP_REG_PTCR 0x60 // Pass-Thru Configuration Register 79 #define AMCC_OP_REG_RANGE_S5920 0x64 // number of operation registers 86 #define AMCC_INT_MASK 0x0000FFFFL 87 #define AMCC_INT_ENB ( 1L << 12 ) 88 #define AMCC_INT_FLAG ( 1L << 17 ) 89 #define AMCC_INT_ACK ( AMCC_INT_ENB | AMCC_INT_FLAG )