mbgtools-lx  4.2.8
amccdefs.h
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1 
2 /**************************************************************************
3  *
4  * $Id: amccdefs.h 1.3 2017/05/10 15:21:33 martin REL_M $
5  *
6  * Copyright (c) Meinberg Funkuhren, Bad Pyrmont, Germany
7  *
8  * Description:
9  * Definitions to be used with AMCC PCI interface chips.
10  *
11  * -----------------------------------------------------------------------
12  * $Log: amccdefs.h $
13  * Revision 1.3 2017/05/10 15:21:33 martin
14  * Tiny cleanup.
15  * Revision 1.2 2007/06/06 10:16:53 martin
16  * Moved some IRQ bit masks here.
17  * Revision 1.1 2000/07/20 09:19:39Z MARTIN
18  * Initial revision
19  *
20  **************************************************************************/
21 
22 #ifndef _AMCCDEFS_H
23 #define _AMCCDEFS_H
24 
25 
26 /* Other headers to be included */
27 
28 
29 #ifdef _AMCCDEFS
30  #define _ext
31 #else
32  #define _ext extern
33 #endif
34 
35 
36 /* Start of header body */
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
42 
43 // The following operation registers are implemented
44 // in the S5933. The registers can be accessed via port
45 // I/O to base_addr_0 + offset as defined below:
46 
47 #define AMCC_OP_REG_OMB1 0x00 // Outgoing Mail Box 1
48 #define AMCC_OP_REG_OMB2 0x04 // Outgoing Mail Box 2
49 #define AMCC_OP_REG_OMB3 0x08 // Outgoing Mail Box 3
50 #define AMCC_OP_REG_OMB4 0x0C // Outgoing Mail Box 4
51 #define AMCC_OP_REG_IMB1 0x10 // Incoming Mail Box 1
52 #define AMCC_OP_REG_IMB2 0x14 // Incoming Mail Box 2
53 #define AMCC_OP_REG_IMB3 0x18 // Incoming Mail Box 3
54 #define AMCC_OP_REG_IMB4 0x1C // Incoming Mail Box 4
55 #define AMCC_OP_REG_FIFO 0x20 // FIFO Register
56 #define AMCC_OP_REG_MWAR 0x24 // Master Write Address Register
57 #define AMCC_OP_REG_MWTC 0x28 // Master Write Transfer Count Register
58 #define AMCC_OP_REG_MRAR 0x2C // Master Read Address Register
59 #define AMCC_OP_REG_MRTC 0x30 // Master Read Transfer Count Register
60 #define AMCC_OP_REG_MBEF 0x34 // Mailbox Empty/Full Status
61 #define AMCC_OP_REG_INTCSR 0x38 // Interrupt Control/Status Register
62 #define AMCC_OP_REG_MCSR 0x3C // Bus Master Control/Status Register
63 
64 #define AMCC_OP_REG_RANGE_S5933 0x40 // number of operation registers
65 
66 
67 
68 // The following operation registers are implemented
69 // in the S5920. The registers can be accessed via port
70 // I/O to base_addr_0 + offset as defined below:
71 
72 #define AMCC_OP_REG_OMB 0x0C // Outgoing Mail Box
73 #define AMCC_OP_REG_IMB 0x1C // Incoming Mail Box
74 #define AMCC_OP_REG_MBEF 0x34 // Mailbox Empty/Full Status
75 #define AMCC_OP_REG_INTCSR 0x38 // Interrupt Control/Status Register
76 #define AMCC_OP_REG_RCR 0x3C // Reset Control Register
77 #define AMCC_OP_REG_PTCR 0x60 // Pass-Thru Configuration Register
78 
79 #define AMCC_OP_REG_RANGE_S5920 0x64 // number of operation registers
80 
81 
82 
83 // The following bit masks are used by the drivers in order to
84 // control interrupts on the PCI bus:
85 
86 #define AMCC_INT_MASK 0x0000FFFFL
87 #define AMCC_INT_ENB ( 1L << 12 )
88 #define AMCC_INT_FLAG ( 1L << 17 )
89 #define AMCC_INT_ACK ( AMCC_INT_ENB | AMCC_INT_FLAG )
90 
91 
92 /* End of header body */
93 
94 #undef _ext
95 
96 
97 /* ----- function prototypes begin ----- */
98 
99 /* This section was generated automatically */
100 /* by MAKEHDR, do not remove the comments. */
101 
102 /* (no header definitions found) */
103 
104 /* ----- function prototypes end ----- */
105 
106 #ifdef __cplusplus
107 }
108 #endif
109 
110 
111 #endif /* _AMCCDEFS_H */