mbgtools-lx  4.2.8
plxdefs.h
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1 
2 /**************************************************************************
3  *
4  * $Id: plxdefs.h 1.5 2017/05/10 15:26:09 martin REL_M $
5  *
6  * Copyright (c) Meinberg Funkuhren, Bad Pyrmont, Germany
7  *
8  * Description:
9  * Definitions to be used with PLX PCI Express interface chips.
10  * Some Meinberg cards use the PLX8311 chip in endpoint mode.
11  *
12  * The PLX8311 chip is combined of a PLX8111 PCIe-to-PCI bridge
13  * plus a PCI-to-Local bus interface combined in a single package.
14  * Thus each card using a PLX8311 implements an additional internal
15  * PCI bus with a single device connected to this bus.
16  *
17  * Each of these devices are individually visible from the PC's
18  * PCI bus and thus provide their own configuration spaces,
19  * configuration EEPROM, etc.
20  *
21  * Care must be taken not to confuse the registers of the PLX8311
22  * with the correspondent registers of the built-in PLX8111 bridge.
23  *
24  * -----------------------------------------------------------------------
25  * $Log: plxdefs.h $
26  * Revision 1.5 2017/05/10 15:26:09 martin
27  * Tiny cleanup.
28  * Revision 1.4 2013/03/15 10:24:09 martin
29  * Renamed register and bit mask definitions to match the names in the data sheet.
30  * Added doxygen comments.
31  * Revision 1.3 2012/10/15 09:21:42Z martin
32  * Added some mailbox register addresses.
33  * Revision 1.2 2010/01/28 15:46:31Z martin
34  * Added PLX8311_REG_CTRL.
35  * Revision 1.1 2007/06/08 07:46:56Z martin
36  * Initial revision.
37  *
38  **************************************************************************/
39 
40 #ifndef _PLXDEFS_H
41 #define _PLXDEFS_H
42 
43 /* Other headers to be included */
44 
45 
46 #ifdef _PLXDEFS
47  #define _ext
48 #else
49  #define _ext extern
50 #endif
51 
52 
53 /* Start of header body */
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
62 #define PCI_DEVICE_ID_PLX_8111 0x8111
63 
64 
93 {
95  // PLX_PECS_LINKSTAT = 0x72, ///< Link status
98 
99  PLX_PECS_EECTL = 0x1004,
101  PLX_PECS_GPIOCTL = 0x1020,
102  PLX_PECS_GPIOSTAT = 0x1024,
103  PLX_PECS_TLPCFG0 = 0x1048,
104 
106 };
107 
108 
109 // Bit masks used with the PLX_PECS_EECTL register.
110 // See chap 18.10 of the manual
111 #define PLX_PECS_EECTL_WRITE_DATA_SHIFT 0
112 #define PLX_PECS_EECTL_READ_DATA_SHIFT 8
113 #define PLX_PECS_EECTL_WRITE_START ( 1UL << 16 )
114 #define PLX_PECS_EECTL_READ_START ( 1UL << 17 )
115 #define PLX_PECS_EECTL_CS_ENB ( 1UL << 18 )
116 #define PLX_PECS_EECTL_BUSY ( 1UL << 19 )
117 #define PLX_PECS_EECTL_VALID ( 1UL << 20 )
118 #define PLX_PECS_EECTL_PRESENT ( 1UL << 21 )
119 #define PLX_PECS_EECTL_CS_ACTIVE ( 1UL << 22 )
120 #define PLX_PECS_EECTL_RELOAD ( 1UL << 31 )
121 
122 // Bit masks used with the PLX_PECS_EECLKFREQ register.
123 #define PLX_PECS_EECLKFREQ_8_3_MHZ 0x02 // 3 LSBs
124 
125 // Bit masks used with the PLX_PECS_GPIOCTL register.
126 #define PLX_PECS_GPIOCTL_GPIO3_DATA ( 1UL << 3 )
127 
128 
129 
138 {
139  PLX_LCS_INTCSR = 0x68,
140  PLX_LCS_CNTRL = 0x6C,
141 
143 };
144 
145 
146 // Bit masks used with the PLX_LCS_CNTRL register.
147 #define PLX_LCS_CNTRL_USERO ( 1UL << 16 )
148 #define PLX_LCS_CNTRL_USERI ( 1UL << 17 )
149 
150 
151 // The following bits must be set in the INTCSR register
152 // to let the local microcontroller be able to generate
153 // interrupts on the PCI bus via the chip's LINTi# line:
154 #define PLX_LCS_INTCSR_INT_ENB ( ( 1UL << 11 ) /* Local Interrupt Input Enable */ \
155  | ( 1UL << 8 ) /* Internal PCI Wire Interrupt Enable */ \
156  )
157 
158 // The bit below signals if an LINTi# interrupt is active:
159 #define PLX_LCS_INTCSR_INT_FLAG ( 1UL << 15 ) /* Local Interrupt Input Active */
160 
161 
162 
163 /* ----- function prototypes begin ----- */
164 
165 /* This section was generated automatically */
166 /* by MAKEHDR, do not remove the comments. */
167 
168 /* (no header definitions found) */
169 
170 /* ----- function prototypes end ----- */
171 
172 #ifdef __cplusplus
173 }
174 #endif
175 
176 /* End of header body */
177 
178 #undef _ext
179 
180 #endif /* _PLXDEFS_H */
General Purpose I/O status.
Definition: plxdefs.h:102
General Purpose I/O control.
Definition: plxdefs.h:101
PLX_LCS_REGS_PCI
Local Configuration Space (LCS) registers.
Definition: plxdefs.h:137
0xEC from local
Definition: plxdefs.h:140
Serial EEPROM control.
Definition: plxdefs.h:99
PLX_PECS_REGS
PLX PCI Express Configuration Space (PECS) registers.
Definition: plxdefs.h:92
PCI capabilities pointer.
Definition: plxdefs.h:94
Main Control Register index.
Definition: plxdefs.h:96
Interrupt control / status.
Definition: plxdefs.h:139
Main Control Register data.
Definition: plxdefs.h:97
TLP controller configuration 0.
Definition: plxdefs.h:103
Serial EEPROM clock frequency control.
Definition: plxdefs.h:100