62 #define PCI_DEVICE_ID_PLX_8111 0x8111 111 #define PLX_PECS_EECTL_WRITE_DATA_SHIFT 0 112 #define PLX_PECS_EECTL_READ_DATA_SHIFT 8 113 #define PLX_PECS_EECTL_WRITE_START ( 1UL << 16 ) 114 #define PLX_PECS_EECTL_READ_START ( 1UL << 17 ) 115 #define PLX_PECS_EECTL_CS_ENB ( 1UL << 18 ) 116 #define PLX_PECS_EECTL_BUSY ( 1UL << 19 ) 117 #define PLX_PECS_EECTL_VALID ( 1UL << 20 ) 118 #define PLX_PECS_EECTL_PRESENT ( 1UL << 21 ) 119 #define PLX_PECS_EECTL_CS_ACTIVE ( 1UL << 22 ) 120 #define PLX_PECS_EECTL_RELOAD ( 1UL << 31 ) 123 #define PLX_PECS_EECLKFREQ_8_3_MHZ 0x02 // 3 LSBs 126 #define PLX_PECS_GPIOCTL_GPIO3_DATA ( 1UL << 3 ) 147 #define PLX_LCS_CNTRL_USERO ( 1UL << 16 ) 148 #define PLX_LCS_CNTRL_USERI ( 1UL << 17 ) 154 #define PLX_LCS_INTCSR_INT_ENB ( ( 1UL << 11 ) \ 159 #define PLX_LCS_INTCSR_INT_FLAG ( 1UL << 15 ) General Purpose I/O status.
General Purpose I/O control.
PLX_LCS_REGS_PCI
Local Configuration Space (LCS) registers.
PLX_PECS_REGS
PLX PCI Express Configuration Space (PECS) registers.
PCI capabilities pointer.
Main Control Register index.
Interrupt control / status.
Main Control Register data.
TLP controller configuration 0.
Serial EEPROM clock frequency control.